In recent years, as solid-state image sensors taking the place of CCDs, CMOS image sensors have attracted attention.
The reason for this is that various problems including the system becoming very complex because dedicated processes are necessary in the manufacture of CCD pixels, a plurality of power-supply voltages being necessary for the operations thereof, and furthermore, a plurality of peripheral ICs needing to be combined and operated, are overcome by using CMOS image sensors.
For manufacturing CMOS image sensors, it is possible to use manufacturing processes that are the same as those used for typical CMOS-type integrated circuits, also driving using a single power source is possible, and furthermore, analog circuits and logic circuits employing CMOS processes can be made to coexist in the same chip. Therefore, CMOS image sensors have a plurality of significant merits, such as it being possible to decrease the number of peripheral ICs.
Regarding output circuits of CCDs, it is usually the case that there is one channel (ch) output using an FD amplifier having a floating diffusion layer (FD).
In contrast, for CMOS image sensors, an FD amplifier is provided for each pixel, and it is usually the case that parallel-column output-types are used in which a certain row within a pixel array is selected and the pixels are simultaneously read in the column direction.
The reason for this is that it is difficult for an FD amplifier arranged in a pixel to obtain sufficient driving performance, and therefore, the data rate needs to be decreased and parallel processing is considered to be advantageous.
Various signal output circuits for this parallel-column output-type CMOS image sensor have been proposed.
As a technique used for reading a pixel signal of a CMOS image sensor, there is a method in which signal charge serving as an optical signal, which is generated by a photoelectric conversion element, such as a photodiode, is temporarily sampled and read out, via a MOS switch arranged in the vicinity thereof, to a capacitor ahead of the MOS switch.
In a sampling circuit, usually, noise having a reverse correlation with a sampling capacitance value is carried. In a pixel, when signal charge is to be transferred to a sampling capacitor, a potential slope is used, and signal charge is completely transferred. Therefore, noise is not generated in this sampling process, but noise is carried when the voltage level of the preceding capacitor is reset to a certain reference value.
As a typical technique for removing this noise, there is correlated double sampling (CDS). This is a technique in which a state (reset level) immediately before signal charge is sampled once is read and stored, then, the signal level after sampling is read, and the signal level is subtracted, thereby removing noise.
There are various specific methods for CDS. One of most advanced forms regarding signal output circuits of parallel-column output-type CMOS image sensors is a type in which an analog-digital (A/D) conversion circuit (ADC (analog digital converter)) is provided for each column, and a pixel signal is extracted as a digital signal.
A CMOS image sensor having such a parallel column-type ADC mounted therein is disclosed in, for example, W. Yang et al. (W. Yang et. Al., “An Integrated 800×600 CMOS Image System,” ISSCC Digest of Technical Papers, pp. 304-305, February, 1999), Japanese Unexamined Patent Application Publication No. 2005-303648, and Japanese Unexamined Patent Application Publication No. 2005-323331.
For example, in the solid-state image sensor disclosed in Japanese Unexamined Patent Application Publication No. 2005-303648, A/D conversion circuit constituted by a counter, a comparator, and a reference voltage generator is used, a reset level is A/D converted by down count, and next, the signal level is A/D converted by up-count while the value is held, thereby performing CDS by differential computation of digital data.
For this, in pixels arranged in a two-dimensional manner, signal processing circuits in which output signal lines thereof are shared in the vertical direction and in which A/D conversion circuit that receives the output signal lines are included are provided for corresponding signal lines, so that large-scale parallel processing for reading pixel signals for one row at the same time is performed, and high-speed image capturing is realized.
However, in the above-described method, a counter circuit exists in each column, and many counters perform counting operations at the time of A/D conversion, thereby presenting a problem in that the operation electrical current thereof is increased. Furthermore, in addition, in order to shorten an A/D conversion time period and perform A/D conversion of a larger number of gradations within a certain time period, it is necessary to increase the count frequency, and this also causes the operation electrical current to increase.
The present invention aims to provide an A/D conversion circuit in which a counter is made to be capable of performing counting at both edges of a clock, up/down count values can be switched while the up/down count values are held, and it is difficult for the duty of the counting operation to become distorted even with the both-edge counting, a solid-state image sensor, and a camera system.